Round-Robin Arbiter Design
نویسنده
چکیده
Round-robin has been used as a fair (non starvation) scheduling policy in many computer applications. This paper presents a novel hardware design of a round-robin arbiter without any misses – It always grants an available resource to one of legitimate requests, which may be very unevenly generated from various sources. The design is modeled in HDL, logically verified and then synthesized targeting an ASIC technology. The speed and cost of this arbiter, compared with other designs, make it promise well for performance improvement in systems with potential non-uniform requests.
منابع مشابه
Hierarchical Round Robin Arbiter for High-Speed, Low-Power, and Scalable Networks-on-Chip
Recently, the Round Robin Arbiter (RRA), a crucial building block for high-speed switches/routers, receives a new attention with the advent of the Networks-on-chip (NoC). In this paper, we revisit the RRA design with NoC as the new target application platform. We propose the Hierarchical Round Robin Arbiter (HRRA) a high-speed, low-power, area-efficient, and scalable RRA for NoC applications, w...
متن کاملDesign of a High-Speed Overlapped Round Robin (ORR) Arbiter
Round robin (RR) arbitration is commonly used for scheduling of cells in high-speed packet switches. In this paper, we present an overlapped RR (ORR) arbiter design that fully overlaps RR polling and cell scheduling. The ORR arbiter achieves 100% throughput even when a cell transfer time is less than a worst case polling, or scheduling, cycle. This is done by scheduling blocks of cells during a...
متن کاملA Deficit Round Robin Input Arbiter for NetFPGA
I have developed a lightweight Deficit Round Robin scheduler for the input arbiter of the NetFPGA router. The design is effective in reducing latency for small packets from one port in the presence of saturating traffic of large packets from another port. The design hides arbitration latency when multiple channels are active and achieves nearly optimal latency for the NetFPGA architecture. The ...
متن کاملA dynamic adaptive arbiter for Network-on-Chip
Network-on-chip (NoC) is considered as a promising paradigm to overcome the communication bottleneck of future multicore systems. As a basic component in on-chip router, arbiter has a big impact on the performance of router. In this paper, we propose a novel dynamically adaptive arbiter which is based on the round robin mechanism. The proposed arbiter detects buffer status of input ports and ch...
متن کاملArea and Delay Minimized Programmable Prefix Arbiters for On-chip Communications
Network-on-chip (NoC) is an effective on-chip communication technique; the core function of the crossbar schedulers used in the routers located into an NoC is arbitration which is required as and when a number of input ports of a router requests for a particular output port. The design of the arbiters is of paramount importance as the parameters like delay and area of the arbiters play a vital ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2006